AMD Kintex UltraScale+ Gen 2 FPGAs introduced

AMD has introduced the AMD Kintex UltraScale+ Gen 2 FPGAs, expanding its mid-range FPGA portfolio to address growing performance, bandwidth and security requirements in data-intensive systems.

The new FPGA family builds on the existing Kintex UltraScale+ platform and introduces updates across memory, I/O and security. According to AMD, the devices are designed to support demanding workloads in imaging, test and measurement, industrial automation and professional 4K and 8K media environments.

Targeting data-intensive workloads

AMD Kintex UltraScale+ Gen 2 FPGAs are positioned to meet complex system requirements across broadcast, industrial, medical and test markets. The devices integrate high-speed transceivers and PCIe Gen4 to support dense 4K and 8K media workflows, including AV-over-IP, multi-stream capture and frame-accurate transport.

For test and measurement systems, the increased memory bandwidth is intended to accelerate pattern generation, fail capture and timing-sensitive operations in semiconductor testing and inspection. The architecture also supports advanced imaging and real-time control use cases, enabling scalable sensor connectivity for machine vision, industrial automation, medical imaging and robotics.

Memory, I/O and migration path

The FPGA family integrates LPDDR4X, LPDDR5 and LPDDR5X memory controllers, delivering higher DDR bandwidth with deterministic performance. AMD said this allows system designers to manage rising data rates while maintaining predictable latency and power efficiency.

AMD also outlined a migration path from Spartan UltraScale+ FPGAs. Designers can begin development using the XCSU200P device and later migrate to AMD Kintex UltraScale+ Gen 2 FPGAs, with availability planned for the fourth quarter of 2026.

Mid-range performance positioning

According to AMD, Kintex UltraScale+ Gen 2 devices deliver significant gains over the previous generation, including up to five times higher memory bandwidth and up to twice the channel density per PCIe interface. The company said these improvements allow higher throughput and lower latency without requiring a move to higher-cost FPGA classes.

Compared with competing platforms, the family offers higher embedded RAM, increased DSP density and substantially higher LPDDR memory bandwidth, while maintaining support for long product lifecycles and regulated environments.

Security and lifecycle support

Security features are integrated directly into the AMD Kintex UltraScale+ Gen 2 FPGAs, including authenticated device operation, bitstream encryption, anti-cloning protections, secure key management and CNSA 2.0–grade cryptography.

The devices are designed for long-term deployment, with planned availability through at least 2045. AMD said this supply assurance is intended to support multi-decade product lifecycles in industrial, medical, broadcast and test equipment, while reducing redesign requirements and supporting regulatory continuity.

Development continuity is maintained through support for AMD Vivado and Vitis tools, along with existing video, Ethernet and connectivity IP.

Availability and next steps

Simulation support for Vivado and Vitis tools is scheduled for the third quarter of 2026. Pre-production XC2KU050P FPGA silicon is expected to sample in the fourth quarter, followed by an evaluation kit based on production silicon later in the same period.

AMD stated that designers seeking early access to PCIe Gen4, hard controllers and security features can begin development using the Spartan UltraScale+ SCU200 evaluation platform.

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