Susmita Majumder and Debanjali Nath of the National Institute of Technology (NIT) Agartala won first place in the Synopsys Analog Design Contest 2014.
The Analog Design Contest was launched in April 2014, with more than 90 students from more than 50 universities participating. Over the course of three months, each team was required to complete a schematic and DRC/LVS clean layout of an LDO voltage regulator. The design had to meet prescribed specifications and be an original work.
For this students were provided with access to Synopsys analog/mixed-signal tools, an iPDK and training on LDO design and the use of the tools. Contest committee members from CDAC Noida, the University of Hyderabad and Synopsys judged the designs based on criteria that include: functionality demonstrated through HSPICE simulations; measure of efficiency, drop-out voltage, quiescent current, load regulation, line regulation and Power Supply Rejection Ratio (PSRR); optimal area of layout that is DRC/LVS clean; and effective use of design productivity features available with the tool flow.
“Participating in this contest offered us a learning opportunity that we would probably never have had otherwise,” said Susmita Majumder. “My team had never used the Custom Designer flow before, but with the training, support and constant interaction that Synopsys provided, we were able to learn how to use the tool and execute the entire LDO design from concept to GDSII in less than three months.”
“Designing and delivering leading-edge ICs requires a robust ecosystem of tools, IP, process technologies, and skilled engineers,” said Uno Nellore, manager of technical support and training at Synopsys India. “By making our broad range of solutions accessible to universities and supporting hands-on programs like the Synopsys Analog Contest, we are helping create a pool of well-trained engineers with skills that semiconductor companies need.”